The invention relates to an integrated circuit data processing apparatus, including:
an instruction memory which is followed by an instruction register for storing of instruction words; PA1 a program sequencer for addressing the instruction memory for cyclically addressing, selectively in dependence of condition signals, a next instruction word address, an arithmetic and logic element for combining, under control of an information contained in the instruction register, two data words applied; PA1 a buffer memory which is associated with the arithmetic and logic element for storing a combination result and/or a data word to be applied to the arithmetic and logic element; PA1 a data memory being addressed by further information contained in the instruction word and whose data inputs and outputs are connected to an output and an input, respectively, of the arithmetic and logic element; PA1 a connection for communication to an environment external to the data processing apparatus; and PA1 a clock generator for cyclically repeatedly generating a sequence of mutually time-shifted clock signals. PA1 generating the sequence control signals, PA1 addressing the address memory and reading a new address for the instruction memory, PA1 reading the addressed instruction word, and PA1 storing the instruction word in the instruction register, PA1 the new address in the instruction address register, and PA1 the sequence control signal in the sequence control register, PA1 is performed in parallel with the sequence composed of: reading the data memory location addressed by the instruction register and the buffer memory location addressed by the sequence control register, PA1 processing the data read as well as generating the new instruction memory address in the address generator in dependence of the contents of the instruction address register and/or the other signals, and PA1 storing the combination result in the data memory or in the buffer memory and storing the new instruction memory address in the address memory, PA1 advancing the sequence counter, PA1 reading the sequence control memory, PA1 writing the sequence control signal read into the further sequence control register, PA1 is performed essentially in parallel with the other two sequences. Thus, the processing steps of each instruction are sub-divided into three groups which are executed at three levels in a time-interleaved manner.